1. Field of the Invention
The present invention relates to a plasma display apparatus and a driving method thereof.
2. Background of the Related Art
In general, a plasma display apparatus displays images by light-emitting phosphors with ultraviolet generated during the discharge of an inert mixed gas such as He+Xe, Ne+Xe or He+Ne+Xe. This plasma display apparatus can be manufactured to be thin and have a large screensize. The picture quality of the plasma display apparatus has improved given recent technological developments.
To implement the gray scales of images, a plasma display apparatus is time-driven with one frame being divided into several sub-fields having a different number of emissions. Each of the sub-fields is divided into a reset period for initializing the entire screen, an address period for selecting a scan line and selecting a discharge cell from the selected scan line and a sustain period for implementing the gray scales depending on the number of discharges.
For example, to display an image with 256 gray scales, a frame period (16.67 ms) corresponding to 1/60 seconds is divided into eight sub-fields (SF1 to SF8), as shown in FIG. 1. Each of the eight sub-fields (SF1 to SF8) is divided into an initialization period, an address period and a sustain period. The initialization period and the address period of each of the sub-fields are the same for every sub-field. The sustain period and the number of sustain pulses allocated thereto increase in the ratio of 2n (n=0,1,2,3,4,5,6,7) in each sub-field.
FIG. 2 schematically shows the arrangements of electrodes of a three-electrode AC surface discharge type plasma display panel (hereinafter, referred to as “P(DP)”) in the related art.
Referring to FIG. 2, the conventional three-electrode AC surface discharge type P(DP) comprises scan electrodes Y1 to Yn and sustain electrodes Z formed on an upper substrate and address electrodes X1 to Xm formed on a lower substrate to intersect the scan electrodes Y1 to Yn and the sustain electrodes Z.
Discharge cells 1 for displaying one of red, green or blue visible rays are disposed at the intersections of the scan electrodes Y1 to Yn, the sustain electrodes Z and the address electrodes X1 to Xm in matrix form.
A dielectric layer (not shown) and an MgO protection layer (not shown) are formed on the upper substrate in which the scan electrodes Y1 to Yn and the sustain electrodes Z are formed.
Barrier ribs for preventing optical and electrical interference among neighboring discharge cells 1 are formed on the lower substrate in which the address electrodes X1 to Xm are formed. Phosphors, which are excited by ultraviolet ray to emit a visible ray, are formed on the surfaces of the lower substrate and the barrier ribs.
An inert mixed gas, such as He+Xe, Ne+Xe or He+Xe+Ne, is injected into discharge spaces partitioned between the upper substrate and the lower substrate of the P(DP).
FIG. 3 shows a driving waveform supplied to the P(DP) as shown in FIG. 2. The driving waveform of FIG. 3 will be described with reference to the wall charge distribution of FIGS. 4a to 4e. 
Referring to FIG. 3, each of the sub-fields (SFn−1, SFn) comprises a reset period (RP) for initializing the discharge cells 1 of the entire screen, an address period (AP) for selecting discharge cells, a sustain period (SP) for sustaining the discharge of selected discharge cells 1, and an erase period (EP) for erasing wall charges within the discharge cells 1.
In the erase period (EP) of the (n−1)th sub-field (SFn−1), an erase ramp waveform (ERR) is applied to the sustain electrodes Z. during the erase period (EP), 0V is applied to the scan electrodes Y and the address electrodes X. The erase ramp waveform (ERR) is a positive ramp waveform whose voltage gradually rises from 0V to a positive sustain voltage (Vs). An erase discharge is generated between the scan electrodes Y and the sustain electrodes Z within on-cells in which the sustain discharge is generated by the erase ramp waveform (ERR). Wall charges within the on-cells are erased by the erase discharge. As a result, each of the discharge cells 1 has the wall charge distribution as shown in FIG. 4a soon after the erase period (EP).
In a set-up period (SU) of the reset period (RP) where the nth sub-field (SFn) begins, a positive ramp waveform (PR) is applied to all the scan electrodes Y, and 0V is applied to the sustain electrodes Z and the address electrodes X. A voltage on the scan electrodes Y gradually rises from the positive sustain voltage (Vs) to a reset voltage (Vr), which is higher than the positive sustain voltage (Vs), by means of the positive ramp waveform (PR) of the set-up period (UP). A dark discharge is generated between the scan electrodes Y and the address electrodes X within the discharge cells of the entire screen as well as between the scan electrodes Y and the sustain electrodes Z by means of the positive ramp waveform (PR).
As a result of the dark discharge, positive wall charges remain on the address electrodes X and the sustain electrodes Z immediately after the set-up period (SU), and negative wall charges remain on the scan electrodes Y, as shown in FIG. 4b. While the dark discharge is generated in the set-up period (SU), a gap voltage (Vg) between the scan electrodes Y and the sustain electrodes Z and a gap voltage between the scan electrodes Y and the address electrodes X are initialized to a voltage close upon a firing voltage (Vf) which can generate a discharge.
In a set-down period (SD) of the reset period (RP) after the set-up period (SU), a negative ramp waveform (NR) is applied to the scan electrodes Y. At the same time, the positive sustain voltage (Vs) is applied to the sustain electrodes Z and 0V is applied to the address electrodes X. A voltage on the scan electrodes Y gradually falls from the positive sustain voltage (Vs) to a negative erase voltage (Ve) by means of the negative ramp waveform (NR).
A dark discharge is generated between the scan electrodes Y and the sustain electrodes Z as well as between the scan electrodes Y and the address electrodes X within the discharge cells of the entire screen by means of the negative ramp waveform (NR). As a result of the dark discharge of the set-down period (SD), the wall charge distribution within each of the discharge cells 1 is changed to an optimal address condition, as shown in FIG. 4c. Except for a predetermined amount of required wall charges, excessive wall charges unnecessary for an address discharge are erased from the scan electrodes Y and the address electrodes X within each of the discharge cells 1.
The polarity of the wall charges on the sustain electrodes Z inverts from a positive polarity to a negative polarity as negative wall charges move from the scan electrodes Y accumulate on the sustain electrodes Z. While the dark discharge is generated in the set-down period (SD) of the reset period (RP), a gap voltage between the scan electrodes Y and the sustain electrodes Z and a gap voltage between the scan electrodes Y and the address electrodes X becomes close to the firing voltage (Vf).
In the address period (AP), while negative scan pulses (−SCNP) are sequentially applied to the scan electrodes Y, a positive data pulse (DP) is applied to the address electrodes X in synchronization with the scan pulse (−SCNP). A voltage of the scan pulse (−SCNP) is a scan voltage (Vsc), which falls from 0V or a negative scan bias voltage (Vyb) to about a 0V to a negative scan voltage (−Vy). A voltage of the data pulse (DP) is a positive data voltage (Va). During the address period (AP), a positive Z bias voltage (Vzb), which is lower than the positive sustain voltage (Vs), is applied to the sustain electrodes Z.
In a state where the gap voltage is adjusted to a voltage of about to the firing voltage (Vf) immediately after the reset period (RP), an address discharge is generated between the scan electrodes Y and the address electrodes X while the gap voltage between the electrodes Y and X exceeds the firing voltage (Vf) within on-cells to which the scan voltage (Vsc) and the data voltage (Va) are applied. The first address discharge between the scan electrode Y and the address electrode X generates priming charged particles within the discharge cells, and thus induces a second discharge between the scan electrodes Y and the sustain electrodes Z, as shown in FIG. 4d. The wall charge distribution within on-cells in which the address discharge is generated is shown in FIG. 4e. 
The wall charge distribution within off-cells in which the address discharge is not generated substantially keeps the state shown in FIG. 4c. 
In the sustain period (SP), sustain pulses (SUSP) of a positive sustain voltage (Vs) are alternately applied to the scan electrodes Y and the sustain electrodes Z. A sustain discharge is generated between the scan electrodes Y and the sustain electrodes Z within on-cells selected by the address discharge every sustain pulse (SUSP) owing to the wall charge distribution of FIG. 4e. However, a discharge is not generated within off-cells during the sustain period. This is because the gap voltage between the scan electrodes Y and the sustain electrodes Z cannot exceed the firing voltage (Vf) when the first positive sustain voltage (Vs) is applied to the scan electrodes Y since the wall charge distribution of the off-cells remains in the state shown in FIG. 4c. 
In the conventional plasma display apparatus, however, several discharges are generated to control the initialization and wall charges of the discharge cells 1 through the erase period (EP) of the (n−1)th sub-field (SFn−1) and the reset period (RP) of the nth sub-field (SFn). Therefore, problems arise because a dark room contrast value decreases and the contrast ratio decreases accordingly. Table 1 below shows the type and number of discharges, which are generated in the erase period (EP) and the reset period (RP) of the previous sub-field (SFn−1) in the conventional plasma display apparatus.
TABLE 1Operating TimeRP of SFnCell StateEP of SFn − 1SUSDOn-cells turned onCounter Discharge (Y-X◯◯in SFn − 1X)Surface Discharge (Y-◯◯◯Z)Off-cells turned offCounter Discharge (Y-X◯◯in SFn − 1X)Surface Discharge (Y-X◯◯Z)
As shown in Table 1, the on-cells that are turned on in the (n−1)th sub-field (SFn−1) generate three surface discharges between the scan electrodes Y and the sustain electrodes Z and two counter discharges between the scan electrodes Y and the address electrodes X, while during the erase period (EP) and the reset period (RP). The off-cells that are turned off in the previous sub-field (SFn) generate two surface discharges between the scan electrodes Y and the sustain electrodes Z and two counter discharges between the scan electrodes Y and the address electrodes X, during the erase period (EP) and the reset period (RP).
Multiple discharges, which are generated in the erase period and in the reset period, increase the amount of light emission in the erase period and in the reset period even though the amount of light emission should be minimized to maintain proper contrast, thereby causing the dark room contrast value to decreases. More particularly, since the amount of light emission in the surface discharge between the scan electrodes Y and the sustain electrodes Z is more than the amount of light emission in the counter discharge between the scan electrodes Y and the address electrodes X, the amount of light in the surface discharge has a substantially adverse effect on the dark room contrast.
In the conventional plasma display apparatus, wall charges are not smoothly erased in the erase period (EP) of the (n−1)th sub-field (SFn−1). Therefore, if negative wall charges are excessively accumulated on the scan electrodes Y, a dark discharge is not generated in the set-up period (SU) of the nth sub-field (SFn). If the dark discharge is not generated in the set-up period (SU) as described above, discharge cells are not initialized. In this case, to generate a discharge in the set-up period, the reset voltage (Vr) should be high.
If a dark discharge is not generated in the set-up period (SU), a condition within the discharge cells immediately after the reset period does not become an optimal address condition. This results in an abnormal discharge or an erroneous discharge.
If positive wall charges are excessively accumulated on the scan electrodes Y soon after the erase period (EP) of the (n−1)th sub-field (SFn−1), a strong discharge is generated when the positive sustain voltage (Vs), i.e., a start voltage of the positive ramp waveform (PR), is applied to the scan electrodes Y in the set-up period (SU) of the nth sub-field (SFn). Therefore, initialization is not uniform in all of the cells. This problem will be described below in detail with reference to FIG. 5.
FIG. 5 shows an externally applied voltage (Vyz) between the scan electrodes Y and the sustain electrodes Z in the set-up period (SU) and a gap voltage (Vg) within a discharge cell. The externally applied voltage (Vyz) indicated by a solid line in FIG. 5 is an external voltage applied to the scan electrodes Y and the sustain electrodes Z, respectively. Since the externally applied voltage (Vyz) of 0V is applied to the sustain electrodes Z, it is substantially the same as a voltage of the positive ramp waveform (PR). In FIG. 5, dotted lines {circle around (1)}, {circle around (2)} and {circle around (3)} indicate gap voltages (Vg) formed in a discharge gas by the wall charges within the discharge cell.
The gap voltages (Vg) are different as indicated by dotted lines {circle around (1)}, {circle around (2)} and {circle around (3)} because the amount of wall charges within the discharge cells is different depending on whether a discharge has occurred in a previous sub-field. The relationship between the externally applied voltage (Vyz) between the scan electrodes Y and the sustain electrodes Z and the gap voltage (Vg) formed in the discharge gas within the discharge cell can be expressed in the following Equation 1.Vyz=Vg+Vw  [Equation 1]
In FIG. 5, the gap voltage (Vg) of {circle around (1)} Defers to a case where wall charges within a discharge cell are sufficiently erased and the wall charges are sufficiently small. The gap voltage (Vg) increases in proportion to the externally applied voltage (Vyz), but generates a dark discharge if the gap voltage is about equal the firing voltage (Vf). The gap voltage within the discharge cells is initialized to the firing voltage (Vf) by the dark discharge.
In FIG. 5, the gap voltage (Vg) of {circle around (2)} refers to a case where a strong discharge is generated during the erase period (EP) of the (n−1)th sub-field (SFn−1) and thus inverts the polarity of the wall charges in the wall charge distribution within the discharge cells. The polarity of wall charges accumulated on the scan electrodes Y soon after the erase period (EP) is inverted to a positive polarity because of the strong discharge.
Such a case is generated when the uniformity of discharge cells is low or the slope of the erase ramp waveform (ERR) is varies as the temperature fluctuates in a large sized PDP. In this case, as the initial gap voltage (Vg) rises too much as indicated by {circle around (2)} of FIG. 5, the gap voltage (Vg) exceeds the firing voltage (Vf) while the positive sustain voltage (Vs) is applied to the scan electrodes Y in the set-up period (SU). Therefore, a strong discharge is generated.
Since the discharge cells are not initialized to the wall charge distribution of an optimal address condition, i.e., the wall charge distribution of FIG. 4c by means of the strong discharge in the set-up period (SU) and the set-down period (SD), an address discharge may be generated in off-cells that should be turned off. In other words, if a strong erase discharge is generated in the erase period prior to the reset period, an erroneous discharge can be generated.
In FIG. 5, the gap voltage (Vg) of {circle around (3)} refers to a case where a wall charge distribution within discharge cells, which are formed as a result of a sustain discharge generated immediately before an erase discharge, remains intact because the erase discharge is not generated or a very weak erase discharge is generated during the erase period (EP) of the (n−1)th sub-field (SFn−1). This will be described in more detail below. As shown in FIG. 3, the last sustain discharge is generated when the sustain pulse (SUSP) is applied to the scan electrodes Y.
As a result of the last sustain discharge, negative wall charges remain on the scan electrodes Y and positive wall charges remain on the sustain electrodes Z. However, although these wall charges must be erased for initialization to be normally performed in a next sub-field, the polarity of the wall charges remains intact if the erase discharge is not generated or a very weak discharge generated.
The reason why the erase discharge is not generated or a very weak erase discharge is generated is that the uniformity of discharge cells in a PDP is very low or the slope of the erase ramp waveform (ERR) has changed as a result of temperature fluctuations. In this case, since the initial gap voltage (Vg) is very low, i.e., a negative polarity as shown in {circle around (3)} of FIG. 5, the gap voltage (Vg) within the discharge cells does not equal the firing voltage (Vf) even if the positive ramp waveform (PR) rises up to the reset voltage (Vr) in the set-up period. Therefore, a dark discharge is not generated in the set-up period (SU) and the set-down period (SD). Consequently, if an erase discharge is not generated or a very weak erase discharge is generated in the erase period prior to the reset period, an erroneous discharge or an abnormal discharge is generated because initialization is not adequately performed.
In the case of {circle around (2)} in FIG. 5, the relation between the gap voltage (Vg) and the firing voltage (Vf) can be expressed in the following Equation 2. In the case of {circle around (3)} in FIG. 5, the relation between the gap voltage (Vg) and the firing voltage (Vf) can be expressed in the following Equation 3.Vgini+Vs>Vf  [Equation 2]Vgini+Vr<Vf  [Equation 3]
where Vgini is an initial gap voltage immediately before the set-up period (SU) as shown in FIG. 5.
In consideration of the above described problem, a gap voltage condition (or a wall voltage condition) for enabling initialization to be normally performed in the erase period (EP) and the reset period (RP) can be expressed in the following Equation 4, which fulfills both the equations 2 and 3.Vf−Vr<Vgini<Vf−Vs  [Equation 4]
If the initial gap voltage (Vgini) does not fulfill the condition of Equation 4 prior to the set-up period (SU), the conventional plasma display apparatus will generate an erroneous discharge, miss-discharge or abnormal discharge, and will have a narrow operational margin. In other words, to secure operational reliability and an operational margin in the conventional plasma display apparatus, an erase operation in the erase period (EP) must be performed. However, the erase operation can be performed abnormally depending on the uniformity of discharge cells and a use temperature of a PDP, as described above.
In the conventional plasma display apparatus, an erroneous discharge, miss-discharge or an abnormal discharge can be generated due to excessive spatial charges occurring under a high-temperature environment and an unstable wall charge distribution due to the amount of active motion of the spatial charges. Therefore, a problem arises because the operational margin decreases. This will be described in detail in connection with FIGS. 6a to 6c. 
The amount of spatial charges generated upon discharge and the amount of motion of the spatial charges under a high-temperature environment, are more than those at room temperature or a low temperature. Therefore, in a sustain discharge of a (n−1)th sub-field (SFn−1), substantial number of spatial charges are generated. Many of the spatial charges 61 within the discharge space remain active even immediately after the set-up period (SU) of the nth sub-field (SFn), as shown in FIG. 6a. 
If the data voltage (Va) is applied to the address electrodes X and the scan voltage (−Vy) is applied to the scan electrodes Y during the address period when there is active motion of the spatial charges 61 within the discharge space as shown in FIG. 6a, the negative spatial charges 61 are recombined with negative wall charges that have accumulated on the scan electrodes Y as a result of the set-up discharge in the set-up period (SU). The negative spatial charges 61 are recombined with positive wall charges that have been accumulated on the address electrodes Y as a result of the set-up discharge of the set-up period (SU), as shown in FIG. 6b. 
As a result, as shown in FIG. 6c, the negative wall charges on the scan electrodes Y, which have been formed by the set-up discharge, and the positive wall charges on the address electrodes X, which have been formed by the set-up discharge, are erased. Although the data voltage (Va) and the scan voltage (−Vy) are applied to the address electrodes X and the scan electrodes Y, the gap voltage (Vg) does not equal the firing voltage (Vf). Therefore, an address discharge is not generated.
Therefore, in the case where the driving waveform as shown in FIG. 3 is applied to a PDP used in a high temperature environment, a problem arises because miss-writing of on-cells is frequently occurs.